Cutting-edge Tutorials
ISCAS 2008 proposes the following 12 tutorials. Tutorials will be presented in parallel sessions on Sunday May 18, 2008. All of attendees are strongly encouraged to register in advance. Each person may select one morning tutorial and/or one afternoon tutorial. No hopping between tutorials is allowed.
To register for a tutorial, please click here.
Morning Session, Sunday May 18, 8:30am-12:00pm
1. Milimeter-Wave CMOS Circuits and Transceivers
Presented by:
Behzad Razavi, University of California, Los Angeles
Location: TBA
2.
Analog Front End Circuits for Medical Imaging
Presented by: Krzysztof Iniewski, Redlen Technologies, Inc.
Location: TBA
3. Digital Microfluidic Biochips: Connecting Biochemistry to Integrated Circuits and Systems
Presented by: Krishnendu Chakrabarty, Duke University
Location: TBA
4. Synchronization Circuits for Multi-Clock Domain SoC
Presented by: Ran Ginosar, Technion-Israel Institute of Technology
Location: TBA
5. Cancelled
6. Perception-based Visual Image and Video Processing
Presented by: Weisi Lin, Nanyang Technological University, Singapore
Location: TBA
Afternoon Session, Sunday May 18, 1:00pm-4:30pm
7. Continuous-Time Delta-Sigma ADCs
Presented by: Richard Schreier, Analog Devices, Inc.
Location: TBA
8. Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links
Presented by: Frank O'Mahony, Intel Circuit Research Lab; Bryan Casper, Intel Circuit Research Lab
Location: TBA
9. Tradeoffs and Optimization in Analog CMOS Design
Presented by: David M. Binkley, University of North Carolina at Charlotte
Location: TBA
10. Sensor Networks: Technologies, Protocols and Applications
Presented by: Anura P. Jayasumana, Colorado State University
Location: TBA
11. Spatial multiplexing (SM) multiple-input multiple-output (MIMO) communication based on multiple antennae
Presented by: Markku Juntti, University of Oulu; Joseph R. Cavallaro, Rice University
Location: TBA
12. Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges
Presented by: Konstantin K. Likharev, Stony Brook University; Garrett S. Rose, Polytechnic University, Brooklyn; Dmitri B. Strukov, Hewlett-Packard Laboratories
Location: TBA
Millimeter-Wave CMOS Circuits and Transceivers
|
Behzad Razavi |
Description
The growing interest in millimeter-wave transceivers for consumer, radar, and imaging applications has motivated research on the use of CMOS technology for frequencies exceeding 60 GHz. It is envisioned that multiple sophisticated millimeter-wave transceivers capable of beamforming will be integrated on a single chip along with massive baseband processing. This tutorial addresses challenges that we face in the design and integration of such systems and describes new device, circuit, and architecture techniques that deal with these challenges. Examples will include 60-GHz CMOS transceiver architectures as well as circuit techniques that allow operation beyond 120 GHz in 90-nm CMOS technology.
Bio
Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on wireless and wireline transceivers, phase-locking phenomena, and data converters. Professor Razavi has received numerous awards for his research and teaching, including the Beatrice Winner Award for Editorial Excellence at the 1994 ISSCC, the best paper award at the 1994 European Solid-State Circuits Conference, the best panel award at the 1995 and 1997 ISSCC, the TRW Innovative Teaching Award in 1997, and the best paper award at the IEEE Custom Integrated Circuits Conference in 1998. He was the co-recipient of both the Jack Kilby Outstanding Student Paper Award and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC and received the Lockheed Martin Excellence in Teaching Award in 2006 and the UCLA faculty Senate Teaching Award in 2007.
Spatial multiplexing (SM) multiple-input multiple-output (MIMO) communication based on multiple antennae
|
Markku Juntti University of Oulu Home Page |
|
Joseph R. Cavallaro Rice University Home Page |
Description
Spatial multiplexing (SM) multiple-input multiple-output (MIMO) communication based on multiple antennae is covered with an emphasis on the transceiver algorithms, architectures, and implementations. Application examples include the third generation (3G) cellular communication systems, its advanced Long Term Evolution (LTE), and Worldwide Interoperability for Microwave Access (WiMAX) systems. Detectors for forward error control (FEC) coded communications are given most emphasis. The main objective is to review the basic concepts and possible techniques of multiple antenna and/or MIMO communications, derive the basic receiver algorithms and introduced list sphere detector (LSD) algorithm, architecture and implementation solutions to approximate the optimal maximum a posteriori (MAP) detectors in FEC coded systems.
Bios
Markku Juntti received his Dr. Sc. (Tech.) degree in Electrical Engineering from University of Oulu, Oulu, Finland in 1997. In 1999-2000 he was with Nokia Networks as a Senior Specialist. Dr. Juntti has been a Professor at University of Oulu since 2000. Dr. Juntti's research interests include communication and information theory, signal processing for wireless communication systems as well as their application in wireless communication system design. He is an author or co-author in some 180 papers as well as a book WCDMA for UMTS published by Wiley. He has given tutorial presentations on CDMA system and receiver design in several international conferences. Dr. Juntti is a senior member of IEEE, and an Associate Editor for the IEEE Transactions on Vehicular Technology. He was a Co-Chair of the TPC of 2006 IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2006).
Joseph R. Cavallaro received the Ph.D. degree in Electrical Engineering from Cornell University in 1988. From 1981 to 1983, he was with AT&T Bell Laboratories, Holmdel, NJ. In 1988, he joined the faculty of Rice University, Houston, Texas, where he is currently a Professor of Electrical and Computer Engineering and Associate Director of the Center for Multimedia Communication. His research interests include DSP and VLSI architectures for applications in wireless communications. During 1996–1997, he served at the USA National Science Foundation as Director of the Prototyping Tools and Methodology Program. During 2005, he was a Nokia Foundation Fellow at the University of Oulu, Finland. He is a Senior Member of the IEEE, and was Co-Chair of the 2004 Signal Processing for Communications Symposium at the IEEE Global Communications Conference (Globcom) and General Co-chair of the 2004 IEEE 15th International Conference on Application-Specific Systems, Architectures and Processors (ASAP).
Analog Front End Circuits for Medical Imaging
|
Krzysztof Iniewski Redlen Technologies, Inc. Home Page |
Description
The ability to peer into the human body is an essential diagnostic tool in medicine for whichvarious imaging techniques are used (ultra-sound, X-ray, CT, MRI, PET and SPECT). Despite their vastly different principles of operation there are numerous commonalities in the processing of the signals received by these imaging detectors: signal amplification, filtering, multiplexing, and analog to digital conversion. This tutorial presents various analog front end circuit techniques used to deal with off-sets, noise sources and processing variations (sensor leakage compensation, chopper stabilization, auto-zeroing, correlated double sampling, gain calibration, temperature compensation). We will also briefly discuss ADC configurations that are suitable for medical applications (slope, pipeline, sigma-delta, and SAR).
Bio
Krzysztof (Kris) Iniewski is managing R&D chip development activities at Redlen Technologies Inc., a start-up company in British Columbia. His research interests are in VLSI circuits for medical imaging and security applications. He is an editor of “VLSI Circuits for the NanoEra: Communications, Imaging and Sensing”, “Wireless Technologies: Circuits, Systems and Devices”, and co-author of “Network Infrastructure and Architecture”. In his career Dr. Iniewski has held management and research positions at the Universiy of Alberta (2004-2006), PMC-Sierra (1995-2003) and the University of Toronto (1988-1994). He has published over 100 research papers and holds 18 international patents.
Sensor Networks: Technologies, Protocols and Applications
|
Anura P. Jayasumana Colorado State University Home Page |
Description
Dense collections of smart sensors, actuators, and processors that self-configure form the basis of a new networking and processing paradigm. We will review sensor networking technologies and protocols, and look at related fundamental issues and limitations. Topics include hardware platforms, standards (802.15.4, Zigbee), OS, algorithms, performance, scalability, and limitations. While emphasis is on wireless sensor networks, we will also address medium and high-speed sensor actuator networks. An array of applications will be used to illustrate capabilities, constraints, and scalability. Concepts of sensor networking can and will significantly alter the way complex systems are designed in areas including environmental monitoring, transport systems, agriculture and security.
Bio
Anura Jayasumana is a Professor of Electrical & Computer Engineering, and Computer Science at Colorado State University. His areas of expertise include Computer and Communication Networks, Optical Networks, and Sensor Networks. He has served extensively as a consultant to industry from startups to Fortune 100 companies, supervised over 60 M.S. and Ph.D. theses, holds two patents, and is a co-author of a book and over 200 papers. His current research span low-end wireless sensor networks to high-end high-bandwidth real-time sensing systems. Awards include Outstanding Faculty of the Year from the Mountain States Council of the American Electronics Association.
Digital Microfluidic Biochips: Connecting Biochemistry to Integrated Circuits and Systems
|
Krishnendu Chakrabarty Duke University Home Page |
Description
This tutorial will provide an overview of droplet-based "digital" microfluidics, technology platforms, and applications followed by computer-aided design (CAD), design-for-testability, and reconfiguration aspects of digital microfluidic biochips. Synthesis tools will be presented to map behavioral descriptions to a digital microfluidic platform, and generate an optimized schedule of bioassay operations, chip layout, and droplet-flow paths. Testing techniques will be described to detect faults after manufacture and during field operation. On-line and off-line reconfiguration techniques will be presented to bypass faults once they are detected. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. The target audience is university researchers/professors, Ph.D. students, and IC designers who are interested in multidisciplinary topics and the emerging area of microfluidic biochips, and who are looking for exciting new application areas for electronic chip/system design and CAD algorithms.
Bio
Krishnendu Chakrabarty received the Ph.D. degree from the University of Michigan, Ann Arbor, in 1995. He is Professor of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the NSF CAREER award, the ONR Young Investigator award, and several best papers awards at IEEE conferences. He is a Fellow of IEEE, a Distinguished Visitor of the IEEE Computer Society (2005-2007), and a Distinguished Lecturer of the IEEE CAS Society (2006-2007). Prof. Chakrabarty serves as Associate Editor of several journals, including IEEE Transactions on CAD/ICAS, IEEE Transactions on VLSI Systems, IEEE Transactions on Biomedical Circuits and Systems, and the ACM Journal on Emerging Technologies in Computing Systems.
Perception-based Visual Image and Video Processing
|
Weisi Lin Nanyang Technological University, Singapore Home Page |
Description
Since the human visual system (HVS) is the ultimate receiver for most images and video, it is desirable to use a perceptual criterion in system design and optimization, instead of the traditional MSE, SNR or PSNR measures. The HVS' characteristics can be turned into advantages for systems. In this tutorial, we discuss the relevant physiological/psychological knowledge, basic computational models (signal decomposition, just-noticeable difference, visual attention, and common artifact detection), different perceptually-driven techniques (for picture quality-evaluation, compression, enhancement, watermarking, communication, retrieval, etc.), early industrial deployment, and possible future research directions.
Bio
Weisi Lin graduated from Zhongshan University, China with the B.Sc (1982) and the M.Sc (1985), and from King’s College, London University with the Ph.D (1992). He researched in several organizations in China, UK and Singapore. Currently, he is an Associate Professor in Computer Engineering, Nanyang Technological University, Singapore. For topics closely related to this tutorial, he holds nine patents, and has published two book chapters, 70 refereed journal/conference papers and 10 contributions to international standardization; he has been the project leader of 5 projects, and maintained active long-term working relationship with industries; he gave invited talks in VPQM06 and ICCCN07, and co-chaired special sessions in ICME06 and IMAP07.
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links
|
Frank O'Mahony Intel Circuit Research Lab Home Page |
|
Bryan Casper Intel Circuit Research Lab Home Page |
Description
The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of our tutorial is to assist I/O circuit and system designers in developing intuitive and practical understandings of I/O clocking tradeoffs at all levels of the link hierarchy from circuit-level implementations to system-level architecture.
Topics covered in this tutorial include:
- Forwarded and embedded clock architectures
- Clock quality and jitter metrics
- Behavioral modeling of clock components
- Statistical link-level analysis techniques
- Techniques for clock synthesis, distribution and recovery
- Circuit implementation details and tradeoffs
- Integrated and external jitter characterization techniques
Bios
Frank O'Mahony received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1997, 2000, and 2004, respectively. His doctoral research focused on resonant clock distribution techniques for high-performance microprocessors. Since 2003 he has been with Intel's Circuit Research Lab in Hillsboro, OR. His research interests include high-speed and low-power data links, clock generation and distribution, and design techniques for low-noise, variation-tolerant clocking and signaling circuits. He received the 2003 Jack Kilby Award for Outstanding Student Paper at ISSCC.
Bryan Casper received the M.S. degree in electrical engineering from Brigham Young University, Provo UT. He is currently leading the high-speed signaling team of Intel?s Circuit Research Lab, Hillsboro, Ore. In 1998, he joined the Performance Microprocessor Division of Intel Corporation and worked on the development of the Pentium and Xeon processors. Since 2000, he has been a circuit researcher responsible for the research, design, validation and characterization of high-speed mixed signal circuits and I/O systems.
Tradeoffs and Optimization in Analog CMOS Design
|
David M. Binkley University of North Carolina at Charlotte Home Page |
Description
The three design choices of drain current, channel width, and channel length required for every MOS transistor greatly complicate analog CMOS design, but provide significant opportunities to optimize circuit performance. Use of the inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This tutorial describes hand expressions and measured data illustrating tradeoffs in MOS device performance, including effective gate-source bias and drain-source saturation voltages, transconductance efficiency, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, and mismatch. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mm CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area. Because of the technology normalization present when using the inversion coefficient, the design optimization methods presented are readily extended to smaller geometry processes. The methods provide design intuition leading towards optimum design, while minimizing trial-and-error simulations.
Bio
David M. Binkley received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from the University of Tennessee, Knoxville. In 2000, he joined the University of North Carolina at Charlotte as a faculty member in the Department of Electrical and Computer Engineering were he conducts research in analog CMOS design methods, including design of micropower, low-noise circuits for neural implants and radiation hardened, deep space applications. Dr. Binkley was cofounder and vice president of integrated circuit development at Concorde Microsystems where he designed CMOS integrated circuits for battery-operated consumer applications and positron emission tomography (PET) medical imaging systems. Prior to that, Dr. Binkley was a senior scientist at CTI PET Systems where he designed discrete and integrated circuits for PET medical imaging systems. Both Concorde Microsystems and CTI PET Systems are now part of Siemens Medical Solutions. Dr. Binkley has given tutorials or invited talks at the Design Automation Conference (DAC), European Conference on Circuit Theory and Design (ECCTD), International Symposium on Circuits and Systems (ISCAS), International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), and was a visiting scientist at the Institute of Electronic Design Automation at the Technical University of Munich. His research will appear in the book, Tradeoffs and Optimization of Analog CMOS Design, John Wiley and Sons, to be published in the winter of 2008. Dr. Binkley is the author of over 65 papers in analog circuit design, holds seven U.S. patents, and has conducted research for DARPA, NASA Jet Propulsion Laboratory, and the National Institutes of Health.
Continuous-Time Delta-Sigma ADCs
|
Richard Schreier Analog Devices, Inc. Home Page |
Description
Delta-sigma micro-tutorial; continuous-time (CT) to discrete-time (DT) transformation in MOD1, MOD2 and higher-order systems; the signal transfer function and inherent-anti-aliasing in CT DS ADCs; conversion of a DT prototype into a CT realization; feedback delay and the use of direct feedback; lowpass and bandpass examples of CT systems; DAC noise and nonlinear dynamics; state-of-the-art in CT DS ADCs.
Bio
Richard Schreier is a Senior Design Engineer in the High Speed Converters group of Analog Devices. He graduated with a Ph.D. from the University of Toronto in 1991 and was a Professor at Oregon State University from 1991-1997. He has been working for Analog Devices sine 1997, first in Wilmington, Massachusetts and now in Toronto, Ontario. He is the author of the freeware delta-sigma toolbox for MATLAB, co-editor (with S.R. Norsworthy and G.C Temes) of "Delta-Sigma Data Converters," co-author (with G.C. Temes) of "Understanding Delta-Sigma Data Converters," and a recipient of the 2002 ISSCC Lewis Winner Best Paper Award as well as the 2006 ISSCC Beatrice Winner Award.
Synchronization Circuits for Multi-Clock Domain SoC
|
Ran Ginosar Technion-Israel Institute of Technology Home Page |
Description
Modern systems on chip (SoC) integrate multiple clock domains. The clocks may run at either the same or different frequencies, and the frequencies may change over time when DVFS is used. Moving data across clock domain boundaries requires synchronization. The traditional two-FF synchronizer is no longer sufficient: it incurs high latency, low throughput, and dissipates power. Advanced synchronization circuits will be presented, which achieve close to “zero latency” and higher throughput at reduced power. Synchronization problems will be characterized and classified into several classes, and appropriate synchronizers will be associated with each class. Simulation, measurement and verification of the synchronizers will be discussed.
Outline:
- Introduction (problem formulation, classifications)
- Clock distribution in multi-clock-domain (MCD) SoC. Clock power, variations, and limitations.
- Metastability and synchronization failures: A novel simplified and clarified form of the theory, with applications to modern synchronizers. Measurement and simulation of failing synchronizers. Circuit and layout implications. Temperature and voltage effects. Computing failure probabilities and MTBF.
- Synchronizers for mutually-asynchronous clocks. Synchronizing data and control. Fast and slow synchronizers. Asynchronous FIFOs. Reset and clock synchronization. DFT and STA implications of synchronizers and MCD. Open research problems.
- Typical synchronization errors and fallacies.
- Formal and informal verification of synchronization circuits.
- Synchronizers for (same frequency) multi-synchronous clocks. Adaptive synchronizers, self compensation for drifting phase. Predictive synchronizers.
- Synchronization of long on-chip interconnects. Synchronization in Networks-on-Chip. Synchronization in DVFS environments.
Bio
Ran Ginosar received his BSc from the Technion and his PhD from Princeton University. After conducting research at AT&T Bell Laboratories, he joined the Technion where he is now an Associate Professor at the Electrical Engineering and Computer Science departments, also heading the VLSI Systems Research Center. Professor Ginosar has been a visiting Associate Professor with the University of Utah and co-initiated the Asynchronous Architecture Research Project at Intel (Oregon), where he worked during a two-year Sabbatical on Intel's asynchronous test chip. He has co-founded a number of VLSI companies. He has published numerous papers and patents on VLSI . His research interests include VLSI architecture, asynchronous logic and synchronization.
Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges
|
Konstantin K. Likharev Stony Brook University Home Page |
|
Garrett S. Rose Polytechnic University, Brooklyn, NY Home Page |
|
Dmitri B. Strukov Hewlett-Packard Laboratories Home Page |
Description
We will review the recent development of hybrid digital semiconductor/ nanoelectronic integrated circuits in which the CMOS stack in complemented with a back-end nanoelectronic add-on, for example a nanowire crossbar with simple, bistable two-terminal devices at each crosspoint. Detailed simulations have shown that such hybrid circuits may extend the exponential (“Moore’s-Law”) progress of digital integrated circuits for 10 to 15 years, and also become the basis of mixed-signal neuromorphic networks for advanced information processing. Recently the work on the hybrid circuits received a strong boost from the experimental demonstration of metal-oxide crosspoint devices, and nanowire crossbars with 15-nm-scale half-pitch.
Bios
Konstantin K. Likharev received the Candidate (Ph.D.) degree in Physics from the Lomonosov Moscow State University, Russia in 1969, and the habilitation degree of Doctor of Sciences from the Higher Attestation Committee of the U.S.S.R. in 1979. From 1969 to 1988 Dr. Likharev was a Staff Scientist of Moscow State University, and from 1989 to 1991 the Head of the Laboratory of Cryoelectronics of that university. In 1991 he assumed a Professorship at Stony Brook University (Distinguished Professor since 2002). During his research career, Dr. Likharev worked in the fields of nonlinear classical and dissipative quantum dynamics, and solid-state physics and electronics, notably including superconductor electronics and nanoelectronics. He is an author of more than 250 original publications, approximately 70 review papers, 2 monographs, and several patents.
Garrett S. Rose received the B.S. degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. From May 2004 through August 2005, he was with the Nanosystems Group at the MITRE Corporation, McLean, VA, where he was involved in the design and simulation of nanoscale systems. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at Polytechnic University, Brooklyn, NY. His current research interests include VLSI circuit design, systems-on-chips, and developing VLSI design methodologies for nanoelectronics with a specific interest in hybrid CMOS/molecular electronics.
Dmitri B. Strukov received the M.S. degree in Applied Physics from Moscow Institute of Physics and Technology, Russia, in 1999, and the M.S. and Ph.D. degrees, both in Electrical Engineering, from Stony Brook University in 2002 and 2006, respectively. From 2000 to 2003 he was with Petaflops Design Laboratory, Stony Brook University, performing simulations of high performance parallel architectures and designing superconductor (RSFQ) circuits. From 2004 till 2007 he was with Prof. Likharev’s Nanoelectronics group, Stony Brook University, where his main focus was digital hybrid CMOS/nano circuit architectures. Since February 2007 he is with QSR Group at HP Labs, Palo Alto, CA, where he is involved in nanoscale device physics research. He is broadly interested in the physical implementation of computation, including device physics, circuit design, and high level architecture, with the emphasis on emerging device technologies.